1. Field of the Invention
This invention relates generally to synchronous dynamic random access memory (SDRAM) device and, more particularly, to a cached SDRAM and a caching policy thereof.
2. Discussion of the Related Art
Turning now to FIG. 1, a block diagram of a standard SDRAM is shown, in particular, a 2Mbit.times.4 I/O.times.2 Bank SDRAM. Other configurations of SDRAMs are also known (e.g., 1Mbit.times.8 I/O.times.2 Bank, 512Mbit.times.16 I/O.times.2 Bank, etc.). The typical SDRAM 10 includes an address buffer 12, first and second memory banks (14A, 14B) and corresponding row decoders (16A, 16B), column decoders (18A, 18B), sense amplifiers (20A, 20B), and data latches (22A, 22B). Data input/output buffers 24 receive data to be written into a memory array (i.e., either array 14A or 14B) and output data read from a memory array (i.e., either array 14A or 14B).
An externally supplied system clock (CLK) signal is input to a clock buffer 26 (CLK Buffer), the CLK signal for providing system timing for the various function blocks of the SDRAM 10. SDRAM 10 inputs are sampled on the rising edge of the CLK signal. An externally supplied clock enable signal (CKE) is input to a clock enable buffer 28 (CKE Buffer). The CKE buffer 28 provides an enable output to the CLK Buffer 26 and to a Self Refresh Clock 30. CKE activates the CLK signal when in a high state and deactivates the CLK signal when low. By deactivating the clock CKE low initiates a Power Down mode, Suspend mode, or a Self Refresh mode. The Self Refresh Clock 30 and a Row Address Counter 32 operate in a standard manner for implementing the Self Refresh mode.
Address buffer 12 receives address inputs, A0-A11, and outputs information via address data lines 34 to the command decoder 36, row decoders (16A, 16B), column decoders (18A, 18B), sequential controls (38A, 38B) and mode register 40. The data input/output buffer 24 provides input/outputs, corresponding to DQ0-DQ3.
The command decoder 36 outputs approximate command signals for executing a desired operation of the SDRAM 10, in accordance with input signals which it receives. Examples of typical SDRAM operations include a Read operation and a Write operation. During a Read operation, upon the receipt of a Read command, the SDRAM 10 reads data from a particular memory location specified by the address received on the address lines. Similarly, during a Write operation, the SDRAM writes data received on the data input/output (I/O) lines DQ0-DQ3 into a particular memory location specified by the address received on the address lines. In conjunction with the carrying out of SDRAM operations, the command decoder 36 receives buffered inputs including a chip select (CS), row address strobe RAS, column address strobe CAS, write enable WE, and a bank select (BS) input. In accordance with a first operation, the command decoder 36 provides a command signal to the row address counter 32 for performing a self refresh operation. In accordance with other operations, the command decoder 36 provides command signals to a mode register 40, row/column select blocks (16A, 16B) for each memory bank (14A, 14B), and sequential control blocks (38A, 38B) for each memory bank, as appropriate for carrying out the desired synchronous memory operation wherein the synchronous memory operation corresponds to a standard SDRAM command decoded by the command decoder on a rising or falling clock edge. The mode register 40, for instance, provides a control signal to a respective sequential control (38A, 38B) of each memory bank (14A, 14B). The sequential control for each memory bank controls respective data latches associated with the respective memory bank. The Mode Register 40 receives input data via address buffer 12 for programming the operating mode, CASLatency, burst type (BT), and burst length as shown in FIG. 2. The row/column select (42A, 42B) for each memory bank (14A, 14B) controls respective row decoders (16A, 16B) and column decoders (18A, 18B) associated with the respective memory bank (14A, 14B). A buffered data mask input (DWM) is connected to the data input/output buffers 24 for selectively masking all or none of the data inputs or data outputs of the SDRAM chip 10. Specific implementations for Read, Write, Refresh, and other typical operations of the SDRAM, as shown in FIG. 1, are known in the art and not further discussed herein.
As discussed above, synchronous DRAM products are generally known in the art. Industry standards for SDRAMs have been established, i.e., electrical and mechanical. Included in the standards for 16Mbit synchronous DRAM products, for example, is a requirement that all of the control, address and data input/output circuits are synchronized with the positive edge of an externally supplied clock. Additionally, prior to any access operation, the CAS latency, burst length, and burst sequence must be programmed into the device by address inputs A0-A9 during a Mode Register Set cycle.
While standard synchronous DRAMS are designed to be flexible through programmability and to provide higher burst rates not achievable with asynchronous DRAMs, unfortunately, a standard SDRAM does not improve the initial latency of a page hit or miss. A page hit occurs during a read cycle when the row being accessed is already being sensed by the sense amplifiers and the memory array or bank is open. A page miss occurs during a read cycle when the row being accessed is not currently being sensed by the sense amplifiers, wherein the memory bank must first be closed, reactivated, refreshed, and reopened. Furthermore, the standard SDRAM does not reduce the penalties caused by the DRAM cycle time (t.sub.RC) and the DRAM precharge time (t.sub.RP). With multiple memory banks, a standard SDRAM does allow the user to perform simultaneous operations on both memory banks in order to hide some of the precharge and cycle time delays. However, this feature is only useful if the data being stored is orderly and can be organized such that the SDRAM can ping-pong between the two open banks uninterrupted. With today's multi-tasking computer operating systems, this is a formidable task. Standard SDRAMs thus suffer some performance limitations including, for instance, an inability to fully utilize the memory bandwidth and further having undesirable system wait states for all memory accesses.